1. Field of the Invention
The present invention relates to a solid-state imaging device, and more particularly relates to a MOS type solid-state imaging device having an amplification transistor included in a pixel.
2. Description of the Background Art
In recent years, a MOS (Metal-Oxide-Semiconductor) type solid-state imaging device used as image information capturing means such as a mobile phone, a digital still camera, a movie camera, and the like is required to realize high resolution, low power consumption, and low cost by reducing a pixel pitch while maintaining high image quality. Along with micronization of pixels, the number of pixels of the MOS type solid-state imaging device is increased, and accordingly, the MOS type solid-state imaging device is expected to read a large amount of pixel information at a high speed and to process images at a high speed.
To realize the requirements and expectations, an improved MOS type solid-state imaging device is increasingly expected which includes, in addition to a pixel region having pixels arranged therein, a high-speed analog-digital (AD) conversion circuit and a DSP (Digital Signal Processor) circuit for processing an image signal obtained through the AD conversion. Therefore, large size circuit blocks need to be arranged outside the pixel region.
Further, due to the micronization of the pixels, an amount of light incident on each pixel is decreased in proportional to an area of the pixel. Consequently, sensitivity per pixel is decreased, and a ratio of a signal level to a noise level, i.e., an S/N ratio, deteriorates. In order to improve the S/N ratio, the noise level needs to be decreased. Among noises generated in a pixel, a 1/f noise generated in an amplification transistor needs to be solved, and it is necessary, along with the micronization of the pixels, to reduce the 1/f noise of the amplification transistor.
Further, due to the micronization of the pixels, an area of a photodiode in a unit pixel is decreased, which leads to a decrease in a maximum charge available from each pixel. Thus, density of an n-type diffusion layer of a photodiode is increased. However, when the density is increased, a potential of the photodiode is raised, which consequently causes a failure in readout of a signal charge accumulated in the photodiode, and thus generates an afterimage. To prevent the afterimage, the density of the n-type diffusion layer of the photodiode is increased, and a voltage to be applied to a readout gate is boosted.
FIG. 1 is a layout configuration of a common MOS type solid-state imaging device. A pixel region 8 is composed of pixels arranged in two-dimensional array, and the pixels in the pixel region 8 are driven by a vertical scanning circuit 1 and a horizontal scanning circuit 3. In the pixel region 8, a signal charge accumulated through photoelectric conversion is amplified by an amplification transistor in each pixel, and is read out to a column circuit 2 as a pixel signal. The column circuit 2 has a noise cancellation function of reducing pixel signal fluctuation which is caused by variation in a threshold value of the pixel amplification transistor, and also has an analog memory function of maintaining a noise-cancelled signal. An analog signal maintained in the column circuit 2 is scanned by the horizontal scanning circuit 3, and then sent to an output amplifier circuit 5. The output amplifier circuit 5 amplifies the analog signal and outputs the amplified output signal from a sensor. A timing pulse for controlling the vertical scanning circuit 1, the column circuit 2, the horizontal scanning circuit 3, and the output amplifier circuit 5 is generated by a timing generation circuit 4. An I/O circuit 7 has a buffer function of inputting a pulse signal for controlling the sensor as a whole, and an output buffer function of outputting a signal or the like so as to supply a sample timing of an output signal to an AFE device or the like which receives the output signal from the solid-state imaging device.
FIG. 2 is a diagram showing, in detail, a circuit configuration including the pixel region 8, the column circuit 2, and the horizontal scanning circuit 3 shown in FIG. 1. FIG. 3 is a diagram showing timing waveforms to illustrate driving of the pixels shown in FIG. 2. With respect to all pixels included in a certain row, when potentials of a readout control line 110 and a reset control line 120 are both set to “H” during a reset period shown in FIG. 3, the photodiode 11 and the floating diffusion 16 are reset. After a completion of an accumulation time, a signal charge is read out. During the readout period, the potential of a row selection signal line is set to “H”. During a first half of the readout period, the potential of the reset control line 120 is set to “H”, the potential of the floating diffusion 16 is reset, and the potential of the reset control line 120 is set to “L”.
A reset potential of the floating diffusion 16 in this state is amplified by the amplification transistor 14, and sent to the column circuit 2 through the vertical common signal line 270. During the second half of the readout period, the potential of the readout control line 110 is set to “H”, and a signal charge of the photodiode 11 is transferred to the floating diffusion 16. Thereafter, the potential of the readout control line 110 returns to “L”.
A readout potential of the floating diffusion 16 in this state, where the signal charge is read out, is amplified by the amplification transistor 14, and sent to the column circuit 2 through the vertical common signal line 270. In the column circuit 2, difference between the reset potential signal and the readout potential signal is obtained to remove a noise content generated due to the variation in the threshold value of the amplification transistor 14. Therefore, in the case of a complete dark condition, there is no charge read out into the floating diffusion 16, and consequently, the reset potential and the readout potential of the floating diffusion 16 completely correspond to each other.
When the amplification transistor 14 does not include the noise content, the difference between the reset potential signal and the readout potential signal, which are sent to the column circuit 2, is zero. However, micronization in a MOS type semiconductor process is being progressed, and it is generally known that a 1/f noise is generated from a micronized MOS type transistor. In the amplification transistor 14, due to the 1/f noise, even in the case of a complete dark condition, the reset potential signal and the readout potential signal, which are amplified by the amplification transistor 14 and sent to the column circuit 2, are different from each other by an amount of the 1/f noise. Therefore, even if the difference is removed in the column circuit 2, a noise content still remains, which leads to deterioration in image quality.
As described in Japanese Laid-Open Patent Publication No. 2006-253316, it is known that the 1/f noise of the MOS transistor can be reduced by thinning a gate oxide film. However, when the gate oxide films of all transistors within a pixel is simply thinned, a withstand voltage of each gate oxide film is decreased due to the thinning of the gate oxide film. Therefore, the gate voltage at the readout transistor 12 needs to be lowered at the time of readout, for example. When the gate voltage is lowered at the time of readout, the readout cannot be conducted sufficiently. Consequently, a maximum charge amount (hereinafter referred to as a saturated charge amount) that can be output from the photodiode 11 decreases, and consequently a dynamic range decreases. Otherwise, due to insufficient readout, a noise so called an afterimage is generated, which causes deterioration in image quality.
In order to solve the decrease in the saturated charge amount, the decrease being caused by a decrease in an area of the photodiode due to the micronization of pixels, the gate voltage of the readout transistor 12 is raised to increase the saturated charge amount. That is, the gate oxide film of the transistor in the pixel cannot be simply thinned. Therefore, Japanese Laid-Open Patent Publication No. 2006-253316 discloses a technique of thickening the gate oxide film of the readout transistor 12, and thinning the gate oxide film of the amplification transistor 14 in a pixel.
As above described, in the solid-state imaging device using two thickness types of gate oxide films for transistors in the pixel region 8, the two thickness types of gate oxide films are also used for transistors in a peripheral circuit, conventionally. Specifically, for an analog circuit such as the column circuit 2 and the output amplifier circuit 5, which amplify a pixel signal and perform noise cancellation, a transistor having a thick gate oxide film (having a thickness of 9 nm, and a gate length of 0.4 um or more, for example) is used, and the analog circuit is driven with a power voltage of 3.3V. On the other hand, for a logic circuit such as the timing generation circuit 4, a transistor of a thin gate oxide film (having a thickness of 5 nm, and a gate length of 0.25 μm, for example) is used, and the logic circuit is driven with a power voltage of 2.5V.
In the analog circuit, since amplification of pixel signals and the like is performed, the dynamic range of operation needs to be increased, and thus a high power voltage is required. On the other hand, in the logic circuit, for the sake of lowering power consumption, the power voltage needs to be lowered. However, when the number of pixels in the solid-state imaging device is increased along with the micronization of the pixels, it is necessary to read out more number of pixel signals within a single frame period, which leads to an increase in a readout frequency and an increase in the power consumption.
In order to solve the problem, the gate oxide film of the amplification transistor 14 in a pixel is further thinned. For example, when the gate oxide film having a thickness of 2 to 3 nm is used, a micro transistor made of the same gate oxide film having a short gate length can be used in a peripheral logic circuit outside the pixel region 8, and the peripheral logic circuit can be driven with a power voltage of 1.2 to 1.5V. Accordingly, it is possible to lower the power consumption.
On the other hand, when the power voltage supplied to the amplification transistor 14 is lowered, the dynamic range is decreased, and amplitude of a pixel signal is also decreased. Therefore, it has been difficult to realize lowering of the power consumption in the peripheral circuit while maintaining the dynamic range within a pixel.
As above described, in the conventional solid-state imaging device, in order to solve an increase in the 1/f noise of the amplification transistor in a pixel and a decrease in the saturated charge amount, which are caused by the micronization of pixels, two thickness types of gate oxide films are used in each pixel. That is, a thick gate oxide film is used for the readout transistor, whereas a thin gate oxide film is used for the amplification transistor.
However, if the two thickness types of gate oxide films are simply used for transistors in the peripheral circuit outside the pixel region, the power voltage of the peripheral logic circuit cannot be lowered. Therefore, it is difficult to achieve lowering of the power consumption, and micro transistors cannot be used. Therefore, it is difficult to cause the peripheral logic circuit to operate at a high speed, and a chip size will be increased since the size of the transistors in the peripheral circuit cannot be decreased.